1. Field of the Invention
The present invention generally relates to a pseudo static random access memory (hereinafter, referred to as “PSRAM”), and more specifically, to a PSRAM having a mode register set (hereinafter, referred to as “MRS”) for setting mode registers at a combined synchronous and asynchronous mode.
2. Description of the Prior Art
Generally, a Dynamic Random Access Memory (hereinafter, referred to as “DRAM”) memorizes information with charges in a cell capacitor, transmits accumulative charges to a corresponding bit line through an access transistor, and reads data amplified by a sense amplifier.
Since a memory cell of the DRAM that comprises one access transistor and one cell capacitor occupies a small area, a memory of high capacity can be embodied with the small area.
Meanwhile, a memory device becomes smaller for high-speed operation, reduction of consumed current and miniaturization of the processing system. As the memory device becomes smaller, a memory cell capacitor also becomes smaller so that storage capacitance of the memory cell capacitor is reduced. As a result, the amount of retention charges becomes smaller although data having the same voltage level are inputted to the capacitor.
In order to compensate the reduction in the amount of retention charges, a refresh operation is periodically performed. In the refresh operation, data stored in the cell capacitor are transmitted to a bit line, amplified in a sense amplifier, and then re-written in the cell capacitor.
As result, when data retention characteristics are degraded in the miniaturized device, a refresh cycle is required to be set short in order to compensate the degradation of the data retention characteristics. However, when the refresh cycle is set short, an external processing unit cannot access the DRAM during the refresh operation, thereby degrading the performance of the processing system. Additionally, the amount of consumed current for performing the refresh operation increases when the refresh cycle becomes short. The short refresh cycle does not satisfies the low standby current condition required in a data retention mode of battery driving portable devices, and is not applied to the battery driving portable devices which require low power consumption.
In order to solve the problem of the refresh operation in the DRAM, a PSRAM has been used to operate the DRAM as a SRAM. In the PSRAM, a cycle for reading and writing data and a refresh cycle for performing a refresh operation are successively performed in one of memory access cycles. In other words, since the refresh operation is performed in one access cycle, the refresh can be hidden to the external access so that the DRAM may be operated as the SRAM seemingly.
FIG. 1 is a block diagram of a conventional PSRAM.
The conventional PSRAM comprises a MRS 2, a mode register control unit 4, a CRE buffer 6, a /CS1 buffer 8, a /WE buffer 10 and an address buffer 12.
The mode register control unit 4 outputs an address buffer control signal REGADDIN, a MRS write signal REGWR and a MRS update signal REGUP in response to an output signal CREIN from the CRE buffer 6, a chip selecting signal CSB outputted from the /CS1 buffer 8 and a write active signal WEB outputted from the /WE buffer 10.
The address buffer 12 directly outputs an address inputted in response to an address buffer control signal REGADDIN without address strobe latch.
FIG. 2 is a circuit diagram of the MRS 2 of FIG. 1.
The MRS 2 comprises a plurality of MRS. Each MRS comprises serially connected registers 14 and 16, inverters IV1 and IV2, and transmission gates TG1 and TG2. The transmission gate TG1 selectively transmits an address ADDREG<0> outputted from the address buffer 12 to a first register 14 in response to the MRS write signal REGWR and a signal inverted by the inverter IV1. The transmission gate TG2 selectively transmits an address outputted from the first register 14 to a second register 16 in response to a MRS update signal REGUP and a signal inverted by the inverter IV2. Here, the register 14 having an inversion latch type includes inverters IV3 and IV4, and the register 16 having an inversion latch type includes inverters IV5 and IV6.
FIG. 3 is a circuit diagram of the mode register control unit 4 of FIG. 1.
The mode register control unit 4 comprises inverters IV7, IV8 and IV9, a NAND gate ND1, a NOR gate NR1 and high pulse generators 18 and 20.
The inverter IV7 inverts the signal CREIN, the inverter IV8 inverts the write active signal WEB and the inverter IV9 inverts the chip selecting signal CSB.
The NAND gate ND1 performs a NAND operation on output signals from the inverters IV8 and IV9.
The NOR gate NR1 performs a NOR operation on output signals from the inverter IV7 and the NAND gate ND1, and outputs an address buffer control signal REGADDIN.
The first high pulse generator 18 generates a MRS update signal REGUP having a high pulse in response to the signal CREIN. The second high pulse generator 20 generates a MRS write signal REGWR having a high pulse in response to the address buffer control signal REGADDIN.
Here, the address buffer control signal REGADDIN is activated to a high level if the signal CREIN is activated to a high level when the chip selecting signal CSB is activated to a low level and the write active signal WEB is activated to a low level. That is, the NAND gate ND1 outputs a low level signal when the chip selecting signal CSB and the write active signal WEB are all at a low level. The NOR gate NR1 outputs a high level signal in response to a low level signal outputted from the NAND gate ND1 when the signal CREIN is at the high level.
The MRS write signal REGWR is generated from the high pulse generator 20 in response to the address buffer control signal REGADDIN. That is, the address buffer control signal REGADDIN is activated to a high level, delayed for a delay time of the first high pulse generator 18, and then the MRS write signal REGWR having a high pulse is generated so that an address REGADD<0:x> outputted from the address buffer 12 is written in the first register 14 of the MRS 2.
The MRS update signal REGUP is generated from the high pulse generator 18 in response to the signal CREIN. When the signal CREIN is inactivated to a low level, the first high pulse generator 18 generates the MRS update signal REGUP having a high pulse so that the address stored in the first register 14 is updated to the second register 16.
Currently, various modes such as a synchronous mode, a asynchronous mode or a combined mode can be simultaneously supported to satisfy various specifications required in product market. However, since the conventional PSRAM is operated at the asynchronous mode, it cannot be used at the combined mode.